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Back-Gate Bias-Controllable Subthreshold Slope of Junctionless Transistors
- Issue Date
- Jul-2025
- Publisher
- Institute of Electrical and Electronics Engineers
- Keywords
- Transistors; Logic gates; Capacitance; Analytical models; Semiconductor device measurement; Mathematical models; Silicon; Equivalent circuits; Subthreshold current; P-n junctions; Analytical model equations; back-gate voltage (V-gb); junctionless transistors (JLTs); subthreshold conduction; subthreshold swing (SS)
- Citation
- IEEE Transactions on Electron Devices, v.72, no.7, pp 3903 - 3906
- Pages
- 4
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Transactions on Electron Devices
- Volume
- 72
- Number
- 7
- Start Page
- 3903
- End Page
- 3906
- ISSN
- 0018-9383
1557-9646
- Abstract
- Junctionless transistors (JLTs) are one of the next-generation logic transistors for sub-3-nm technology nodes with several advantages, including very simple structure, no p-n junctions at source and drain, and bulk conduction-based operation. In this work, back-gate voltage (V-gb) influenced subthreshold conduction mechanism of JLTs was investigated in detail. The subthreshold swing (SS) in JLTs was clearly improved with applying a negative V-gb, since the effective channel thickness of JLT was controlled by V-gb. The experimental results were verified by analytical model equations and numerical simulation. Those results provide a key information for developing low-power and energy-efficient applications with JLTs.
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