Hole Trap Extraction in Charge Trap Layer of 3-D nand Flash Memory

Abstract

Hole trap profiles in the charge trap layer (CTL) of 3-D NAND flash memory are characterized using a newly proposed bias-induced hole trap extraction (BITE) technique. At 400 K, the appropriate emission bias (Vemit) regimes are determined by analyzing emission rates to ensure that the Poole–Frenkel (PF) emission, followed by band-to-band (BB) tunneling, constitutes the dominant hole emission mechanisms. The hole trap distribution is quantitatively extracted from time-dependent charge loss characteristics using a retention model formulated in cylin drical coordinates. The resulting trap profile shows a Gaussian-like distribution with the peak density at 4.3×1018 cm–3 · eV–1 at 0.87 eV. As the measurement tempera ture decreases, the trap density at deeper energy levels declines, which is attributed to the increasing contribution of the trap-to-band (TB) emission mechanism.