Decomposition of Charge Loss Mechanisms in 3-D Nand Flash Memory: Impact of Cell Dimension via High-Temperature Long-Term Retention Characteristics
- Authors
- Park, Jounghun; Yoon, Gilsang; Go, Donghyun; Kim, Donghwi; Sagong, Hyun Chul; Kim, Jungsik; Lee, Jeong-Soo
- Issue Date
- Oct-2024
- Publisher
- Institute of Electrical and Electronics Engineers
- Keywords
- Tunneling; Logic gates; Flash memories; Attenuation; Electron traps; Electrons; Voltage measurement; 3-D NAND flash memory; charge loss mechanism; high-temperature retention characteristic
- Citation
- IEEE Transactions on Electron Devices, v.71, no.10, pp 6040 - 6048
- Pages
- 9
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Transactions on Electron Devices
- Volume
- 71
- Number
- 10
- Start Page
- 6040
- End Page
- 6048
- URI
- https://scholarworks.gnu.ac.kr/handle/sw.gnu/74231
- DOI
- 10.1109/TED.2024.3449251
- ISSN
- 0018-9383
1557-9646
- Abstract
- Decompositions of charge loss mechanisms in 3-D NAND flash memory with two different cell structures have been performed using high-temperature retention characteristics. It calculates emission rates of trap-to-band tunneling (TB) and band-to-trap tunneling (BT) to determine the dominant tunneling mechanisms. The lateral migration (LM) component is separated into the LM of holes (LMH) and electrons (LME) using the technology-computer-aided design (TCAD) simulation. The thicker blocking layer could lead to decreased vertical charge loss, and the shorter spacer could enhance the LM components.
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