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Decomposition of Charge Loss Mechanisms in 3-D Nand Flash Memory: Impact of Cell Dimension via High-Temperature Long-Term Retention Characteristics
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Park, Jounghun | - |
| dc.contributor.author | Yoon, Gilsang | - |
| dc.contributor.author | Go, Donghyun | - |
| dc.contributor.author | Kim, Donghwi | - |
| dc.contributor.author | Sagong, Hyun Chul | - |
| dc.contributor.author | Kim, Jungsik | - |
| dc.contributor.author | Lee, Jeong-Soo | - |
| dc.date.accessioned | 2024-12-03T05:00:45Z | - |
| dc.date.available | 2024-12-03T05:00:45Z | - |
| dc.date.issued | 2024-10 | - |
| dc.identifier.issn | 0018-9383 | - |
| dc.identifier.issn | 1557-9646 | - |
| dc.identifier.uri | https://scholarworks.gnu.ac.kr/handle/sw.gnu/74231 | - |
| dc.description.abstract | Decompositions of charge loss mechanisms in 3-D NAND flash memory with two different cell structures have been performed using high-temperature retention characteristics. It calculates emission rates of trap-to-band tunneling (TB) and band-to-trap tunneling (BT) to determine the dominant tunneling mechanisms. The lateral migration (LM) component is separated into the LM of holes (LMH) and electrons (LME) using the technology-computer-aided design (TCAD) simulation. The thicker blocking layer could lead to decreased vertical charge loss, and the shorter spacer could enhance the LM components. | - |
| dc.format.extent | 9 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.title | Decomposition of Charge Loss Mechanisms in 3-D Nand Flash Memory: Impact of Cell Dimension via High-Temperature Long-Term Retention Characteristics | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/TED.2024.3449251 | - |
| dc.identifier.scopusid | 2-s2.0-85205291263 | - |
| dc.identifier.wosid | 001308149400001 | - |
| dc.identifier.bibliographicCitation | IEEE Transactions on Electron Devices, v.71, no.10, pp 6040 - 6048 | - |
| dc.citation.title | IEEE Transactions on Electron Devices | - |
| dc.citation.volume | 71 | - |
| dc.citation.number | 10 | - |
| dc.citation.startPage | 6040 | - |
| dc.citation.endPage | 6048 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Physics | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.subject.keywordPlus | LATERAL MIGRATION | - |
| dc.subject.keywordPlus | OPERATION | - |
| dc.subject.keywordPlus | MODEL | - |
| dc.subject.keywordPlus | SIMULATION | - |
| dc.subject.keywordPlus | DEVICES | - |
| dc.subject.keywordAuthor | Tunneling | - |
| dc.subject.keywordAuthor | Logic gates | - |
| dc.subject.keywordAuthor | Flash memories | - |
| dc.subject.keywordAuthor | Attenuation | - |
| dc.subject.keywordAuthor | Electron traps | - |
| dc.subject.keywordAuthor | Electrons | - |
| dc.subject.keywordAuthor | Voltage measurement | - |
| dc.subject.keywordAuthor | 3-D NAND flash memory | - |
| dc.subject.keywordAuthor | charge loss mechanism | - |
| dc.subject.keywordAuthor | high-temperature retention characteristic | - |
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