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Abnormal Operation of 6-T SRAM based on Nanosheet FET due to Total Ionizing Doseopen access

Authors
Ha, JonghyeonBang, MinjiSuh, MinkiLee, DabokRyu, MinsangHan, Jin-WooSagong, HyunchulLee, HojoonKim, Jungsik
Issue Date
Sep-2025
Publisher
Institute of Electrical and Electronics Engineers Inc.
Keywords
6-T SRAM; Gate-all-around (GAA) structures; nanosheet FET (NSFET); technology computer aided design (TCAD); total ionizing dose (TID)
Citation
IEEE Access, v.13, pp 159639 - 159648
Pages
10
Indexed
SCIE
SCOPUS
Journal Title
IEEE Access
Volume
13
Start Page
159639
End Page
159648
URI
https://scholarworks.gnu.ac.kr/handle/sw.gnu/80129
DOI
10.1109/ACCESS.2025.3607964
ISSN
2169-3536
2169-3536
Abstract
This study investigates the total ionizing dose (TID) effect on the six-transistor static random access memory (6-T SRAM) consisting of a novel device, a nanosheet field effect transistor (NSFET). Via technology computer-aided design, we simulate the hold, read, and write static noise margin (HSNM, RSNM, and WSNM) degradations by the oxide trap, using stationary simulation. In the stationary simulation, the HSNM and RSNM decrease about 75% and bit flip occurs under the oxide trap conditions, respectively. The voltage stored at the VCH (VCL) node reduces owing to the leakage current of the pull-down (PD) transistors. The detail degradation mechanism for the SRAM operation (hold/read/write) problems due to the oxide trap is confirmed through the time-dependent simulations. In the read operations, the leakage current at PD transistors causes a bit flip of the CH node. Moreover, the CH node voltage decreases under hold and write operations (ΔVCH = 15.7% and 14%). Significantly, when the adjacent cell (word-line (WL)2) of the target cell (WL1) operates to write data (VBL down from VDD to 0), the voltage drop at the target cell (WL1) CH node (decreased by 23.3%) is enhanced under hold operation of the target cell. To mitigate the effects of oxide trap that cause electrical characteristic degradation in NSFET 6-T SRAM, we applied a partial dielectric isolation (PDI) structure that locally deposits an oxide (SiO2) on the bottom of the source/drain (S/D). SRAM cells incorporating the proposed PDI technique demonstrated that variations in SNM caused by oxide trap were suppressed to less than 1% across read, write, and hold operations. Additionally, through time-dependent electrical characteristic analysis, it was confirmed that the potential changes in Vch and Vcl converge 1% under various operation modes and adjacent cell activation conditions, thereby demonstrating the effective blocking of the effects of oxide trap occurring in the shallow trench isolation (STI) region.
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