Surround Gate Transistor With Epitaxially Grown Si Pillar and Simulation Study on Soft Error and Rowhammer Tolerance for DRAM
- Han, Jin-Woo; Kim, Jungsik; Beery, Dafna; Bozdag, K. Deniz; Cuevas, Peter; Levi, Amitay; Tain, Irwin; Tran, Khai; Walker, Andrew J.; Palayam, Senthil Vadakupudhu; Arreghini, Antonio; Furnemont, Arnaud; Meyyappan, M.
- Issue Date
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Epitaxial growth; rowhammer; soft-error; surround gate transistor (SGT); TCAD simulation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, v.68, no.2, pp.529 - 534
- Journal Title
- IEEE TRANSACTIONS ON ELECTRON DEVICES
- Start Page
- End Page
- A new dynamic random access memory (DRAM) memory cell transistor is fabricated, and its soft-error immunity and rowhammer tolerance are studied. The vertical channel is formed by selective epitaxial growth of silicon pillar, and the surround gate forms a fully depleted (FD) channel, which can suppress floating-body effects, such as hysteresis. A TCAD simulation study compares this device and conventional bulk saddle FinFET in terms of soft error immunity and rowhammer tolerance. The confined channel limits soft error because of its thin channel volume for charge generation due to alpha and neutron particles. The surround gate device is inherently free from rowhammer attack as each silicon body of any memory cell transistor is fully isolated from neighboring word lines.
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