Detailed Information
Cited 0 time in 
Cited 0 time in 
Cited 0 time in
Metadata Downloads
이중 NAND 플래시 구조의 버퍼시스템에서 효율적 버퍼 크기The Efficient Buffer Size in A Dual Flash Memory Structure with Buffer System
- Other Titles
- The Efficient Buffer Size in A Dual Flash Memory Structure with Buffer System
- Issue Date
- 2011
- Publisher
- 대한임베디드공학회
- Keywords
- Flash memory; characteristics of instruction and data; dual structure; cache memory
- Citation
- 대한임베디드공학회논문지, v.6, no.6, pp 383 - 391
- Pages
- 9
- Indexed
- KCICANDI
- Journal Title
- 대한임베디드공학회논문지
- Volume
- 6
- Number
- 6
- Start Page
- 383
- End Page
- 391
- ISSN
- 1975-5066
- Abstract
- As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - 공과대학 > 제어계측공학과 > Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.