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이중 NAND 플래시 구조의 버퍼시스템에서 효율적 버퍼 크기
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 정보성 | - |
| dc.contributor.author | 이정훈 | - |
| dc.date.accessioned | 2022-12-27T03:19:50Z | - |
| dc.date.available | 2022-12-27T03:19:50Z | - |
| dc.date.issued | 2011 | - |
| dc.identifier.issn | 1975-5066 | - |
| dc.identifier.uri | https://scholarworks.gnu.ac.kr/handle/sw.gnu/24083 | - |
| dc.description.abstract | As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash. | - |
| dc.format.extent | 9 | - |
| dc.language | 한국어 | - |
| dc.language.iso | KOR | - |
| dc.publisher | 대한임베디드공학회 | - |
| dc.title | 이중 NAND 플래시 구조의 버퍼시스템에서 효율적 버퍼 크기 | - |
| dc.title.alternative | The Efficient Buffer Size in A Dual Flash Memory Structure with Buffer System | - |
| dc.type | Article | - |
| dc.publisher.location | 대한민국 | - |
| dc.identifier.bibliographicCitation | 대한임베디드공학회논문지, v.6, no.6, pp 383 - 391 | - |
| dc.citation.title | 대한임베디드공학회논문지 | - |
| dc.citation.volume | 6 | - |
| dc.citation.number | 6 | - |
| dc.citation.startPage | 383 | - |
| dc.citation.endPage | 391 | - |
| dc.identifier.kciid | ART001617955 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | kciCandi | - |
| dc.subject.keywordAuthor | Flash memory | - |
| dc.subject.keywordAuthor | characteristics of instruction and data | - |
| dc.subject.keywordAuthor | dual structure | - |
| dc.subject.keywordAuthor | cache memory | - |
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