High performance and low power TLB structure

Abstract

The goal of this research is to design a simple but high performance and low power TLB system for embedded processors. The most common page size of TLB is still a 4KB and this page size has been used for virtual memory since the sixties. Choosing the best page size for virtual memory requires considering several factors. A smaller page size reduces the amount of internal fragmentation. On the other hand, a large page needs smaller page table. In other to overcome these drawbacks, we propose a new structure of TLB supporting two page sizes to obtain the effect of multiple page sizes with high performance and at low cost without any operating system support. Also in order to reduce power consumption, we divide one TLB space into two sub-TLBs, where these two separate TLB structures are merged into the TLB with two pages. Conclusively, the proposed TLB is designed as a low power and high performance TLB structure for embedded processors. It is shown that the power consumption and the average memory access time can be reduced by around 46% and 20% compared with the conventional fully associative TLB with 64 entries respectively. ?2013 International Information Institute.