Hole Trap Extraction in Charge Trap Layer of 3-D nand Flash Memory
  • Go, Donghyun
  • Park, Jounghun
  • Kim, Donghwi
  • Ju, Jinuk
  • Kim, Seungjae
  • ... Kim, Jungsik
  • 외 1명
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초록

Hole trap profiles in the charge trap layer (CTL) of 3-D NAND flash memory are characterized using a newly proposed bias-induced hole trap extraction (BITE) technique. At 400 K, the appropriate emission bias (Vemit) regimes are determined by analyzing emission rates to ensure that the Poole–Frenkel (PF) emission, followed by band-to-band (BB) tunneling, constitutes the dominant hole emission mechanisms. The hole trap distribution is quantitatively extracted from time-dependent charge loss characteristics using a retention model formulated in cylin drical coordinates. The resulting trap profile shows a Gaussian-like distribution with the peak density at 4.3×1018 cm–3 · eV–1 at 0.87 eV. As the measurement tempera ture decreases, the trap density at deeper energy levels declines, which is attributed to the increasing contribution of the trap-to-band (TB) emission mechanism.

키워드

3-D NANDhole traphole tunnelingPoole–Frenkel (PF)silicon nitrideRETENTIONNITRIDEDEVICESOXIDEOPERATIONMODEL
제목
Hole Trap Extraction in Charge Trap Layer of 3-D nand Flash Memory
저자
Go, DonghyunPark, JounghunKim, DonghwiJu, JinukKim, SeungjaeKim, JungsikLee, Jeong-Soo
DOI
10.1109/TED.2025.3642859
발행일
2026-02
유형
Article
저널명
IEEE Transactions on Electron Devices
73
2
페이지
788 ~ 793