Cited 10 time in
Bistaggered Contact Geometry for Symmetric Dual-Gate Organic TFTs
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kwon, Jimin | - |
| dc.contributor.author | Jung, Sungyeop | - |
| dc.contributor.author | Kim, Yun-Hi | - |
| dc.contributor.author | Jung, Sungjune | - |
| dc.date.accessioned | 2022-12-26T14:47:21Z | - |
| dc.date.available | 2022-12-26T14:47:21Z | - |
| dc.date.issued | 2019-07 | - |
| dc.identifier.issn | 0018-9383 | - |
| dc.identifier.issn | 1557-9646 | - |
| dc.identifier.uri | https://scholarworks.gnu.ac.kr/handle/sw.gnu/9004 | - |
| dc.description.abstract | This transaction proposes a symmetric bistaggered dual-gate organic thin-film transistor (TFT) to minimize the difference between the top and bottom channel current characteristics and demonstrates it through experiment and 2-D simulation. In dual-gate organic TFTs, asymmetric top and bottom channel currents are mainly a result of their asymmetric contact geometry. To address this geometric limitation, the contact electrodes were sandwiched between the two organic semiconductor layers to be placed in a staggered position to both top and bottom gates. Two-way current crowding at the bistaggered contact electrodes leads to high-charge injection efficiency in both channels. | - |
| dc.format.extent | 6 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.title | Bistaggered Contact Geometry for Symmetric Dual-Gate Organic TFTs | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/TED.2019.2917013 | - |
| dc.identifier.scopusid | 2-s2.0-85067615190 | - |
| dc.identifier.wosid | 000472184900040 | - |
| dc.identifier.bibliographicCitation | IEEE Transactions on Electron Devices, v.66, no.7, pp 3118 - 3123 | - |
| dc.citation.title | IEEE Transactions on Electron Devices | - |
| dc.citation.volume | 66 | - |
| dc.citation.number | 7 | - |
| dc.citation.startPage | 3118 | - |
| dc.citation.endPage | 3123 | - |
| dc.type.docType | Article | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | sci | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Physics | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
| dc.subject.keywordPlus | THIN-FILM TRANSISTORS | - |
| dc.subject.keywordPlus | INTEGRATED-CIRCUITS | - |
| dc.subject.keywordAuthor | 2-D simulation | - |
| dc.subject.keywordAuthor | contact resistance | - |
| dc.subject.keywordAuthor | device geometry | - |
| dc.subject.keywordAuthor | independent gate control | - |
| dc.subject.keywordAuthor | thin-film transistors (TFTs) | - |
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