A Fault-Tolerant Architecture of PCI-Express Bus for Avionics Systems

Abstract

Avionics systems that use the PCI-Express bus unfortunately cannot use at least one I/O device if the bus fails, because the I/O device is connected to CPU through only one PCI-Express channel. This paper presents a fault-tolerant architecture of the PCI-Express bus for avionics systems, which tolerates one channel failure with help of the other redundant channel that has not been failed. In this architecture, each redundant PCI-Express channel connects a corresponding port of CPU to each switch logic of channels to provide each I/O device through a switched fault-tolerant channel. This paper includes the results of experimentation to show that the architecture detects the faulty condition in real time and switches the channel to the other redundant channel which has not been failed, when the architecture meets a failure.