A Thyristor-Structured-Based Low-Power Demodulator Circuit for High Reliability and Short-Circuit Current Reduction
- Authors
- Chae, Donggeon; Jung, Wanyeong; Kim, Kihyun; Seok, Wonil; Shim, Minseob
- Issue Date
- Apr-2025
- Publisher
- Institute of Electrical and Electronics Engineers
- Keywords
- Demodulation; Noise; Isolators; Delays; Pulse width modulation; Gate drivers; MOSFET; Short-circuit currents; Propagation delay; Inverters; Demodulator; gate driver IC; low power consumption; signal isolator; silicon carbide (SiC); wide bandgap (WBG) power semiconductor
- Citation
- IEEE Transactions on Power Electronics, v.40, no.4, pp 4740 - 4746
- Pages
- 7
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Transactions on Power Electronics
- Volume
- 40
- Number
- 4
- Start Page
- 4740
- End Page
- 4746
- URI
- https://scholarworks.gnu.ac.kr/handle/sw.gnu/77149
- DOI
- 10.1109/TPEL.2024.3520548
- ISSN
- 0885-8993
1941-0107
- Abstract
- Wide-bandgap (WBG) devices, such as silicon carbide and gallium nitride, offer higher switching frequencies and power density compared to traditional silicon insulated gate bipolar transistors, making them suited for high-voltage and high-power-density applications. However, in systems with multiple WBG devices, large variations in source voltages of each gate driver circuit not only necessitate signal isolators to indirectly transmit control signals but also require effective modulation and demodulation techniques to ensure the reliability of signal transmission. Therefore, this letter proposes a low-power demodulator circuit that reduces both malfunctions from external noise during demodulation and the propagation delay difference between rising and falling edges. By utilizing leakage currents and employing thyristor structures, the circuit achieves an average current consumption under 37 mu A at a 100-MHz input modulated signal, representing a 43% reduction compared to conventional structures. In addition, it suppresses the difference in propagation delay between rising and falling edges to below 3.5%, even when the operating temperature varies from 0 degrees C to 100 degrees C. The proposed circuit was fabricated in the 180-nm bipolar-CMOS-DMOS (BCDMOS) process, and the chip area is 1584 mu m(2).
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