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A Control Strategy for Suppressing Zero-Crossing Current of Single-Phase Half-Bridge Active Neutral-Point-Clamped Three-Level Inverteropen access

Authors
Lee, Gi-YoungKim, Chul-MinHan, JunghoKim, Jong-Soo
Issue Date
Oct-2024
Publisher
MDPI AG
Keywords
multi-level inverters; zero-crossing current; active neutral-point-clamped inverter; DSP
Citation
Electronics (Basel), v.13, no.19
Indexed
SCIE
SCOPUS
Journal Title
Electronics (Basel)
Volume
13
Number
19
URI
https://scholarworks.gnu.ac.kr/handle/sw.gnu/74490
DOI
10.3390/electronics13193929
ISSN
2079-9292
2079-9292
Abstract
Multi-level inverters have characteristics suitable for high-voltage and high-power applications through various topology configurations. These reduce harmonic distortion and improve the quality of the output waveform by generating a multi-level output voltage waveform. In particular, an active neutral-point-clamped topology is one of the multi-level inverters advantageous for high-power and medium-voltage applications. It has the advantage of controlling the output waveform more precisely by actively clamping the neutral point using an active switch and diode. However, it has a problem, which is that an unwanted zero-crossing current may occur if an inaccurate switching signal is applied at the time when the polarity of the output voltage changes. In this paper, a control strategy to suppress the zero-crossing current of a single-phase half-bridge three-level active neutral-point-clamped inverter is proposed. The operating principle of a single-phase half-bridge three-level active neutral-point-clamped inverter is identified through an operation mode analysis. In addition, how the switching signal is reflected in an actual digital signal processor is analyzed to determine the situation in which the zero-crossing current occurs. Through this, a control strategy capable of suppressing zero-crossing current is designed. The proposed method prevents a zero-crossing current by appropriately modifying the update timing of reference voltages at the point where the polarity of the output changes. The validity of the proposed method is verified through simulation and experiments. Based on the proposed method, the total harmonic distortion of the output current is significantly reduced from 12.15% to 4.59% in a full-load situation.
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IT공과대학 (전기공학과)
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