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Mitigation of Single Event Upset Effects in Nanosheet FET 6T SRAM Cell

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dc.contributor.authorBang, Minji-
dc.contributor.authorHa, Jonghyeon-
dc.contributor.authorSuh, Minki-
dc.contributor.authorLee, Dabok-
dc.contributor.authorRyu, Minsang-
dc.contributor.authorHan, Jin-Woo-
dc.contributor.authorSagong, Hyunchul-
dc.contributor.authorLee, Hojoon-
dc.contributor.authorKim, Jungsik-
dc.date.accessioned2024-12-03T04:30:53Z-
dc.date.available2024-12-03T04:30:53Z-
dc.date.issued2024-09-
dc.identifier.issn2169-3536-
dc.identifier.issn2169-3536-
dc.identifier.urihttps://scholarworks.gnu.ac.kr/handle/sw.gnu/73990-
dc.description.abstractThe effects of single event upset (SEU) by alpha particles and heavy ions on the data flip of a 3 nm technology node gate-all-around (GAA) nanosheet field-effect transistor (NSFET) 6T static random access memory (SRAM) cell was studied through technology computer-aided design (TCAD) simulations. It was found that the sensitivity to radiation in the 'off' pull-down transistor varies depending on the position of the alpha particle and heavy ions in the incident. The most significant radiation-induced increase in electron density occurs at the drain-channel junction. Heavy ion strikes lead to the lowest threshold linear energy transfer (LETth) value during the hold operation compared to read and write operations. The partial bottom dielectric isolation (PDI) scheme demonstrates lower radiation sensitivity than the conventional scheme, as the PDI layer acts as a physical barrier preventing charge migration from the substrate to the drain. © 2013 IEEE.-
dc.format.extent9-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleMitigation of Single Event Upset Effects in Nanosheet FET 6T SRAM Cell-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/ACCESS.2024.3457750-
dc.identifier.scopusid2-s2.0-85204126511-
dc.identifier.wosid001320458600001-
dc.identifier.bibliographicCitationIEEE Access, v.12, pp 130347 - 130355-
dc.citation.titleIEEE Access-
dc.citation.volume12-
dc.citation.startPage130347-
dc.citation.endPage130355-
dc.type.docTypeArticle-
dc.description.isOpenAccessY-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaTelecommunications-
dc.relation.journalWebOfScienceCategoryComputer Science, Information Systems-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryTelecommunications-
dc.subject.keywordAuthorGate-all-around (GAA)-
dc.subject.keywordAuthornanosheet field-effect transistor (NSFET)-
dc.subject.keywordAuthorsingle event upset (SEU)-
dc.subject.keywordAuthorSRAM-
dc.subject.keywordAuthorTCAD simulation-
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