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Parallelizing SHA-1
- Authors
- Lee, Hu-Ung; Lee, Seongjin; Kim, Jae-Woon; Youjip, Won
- Issue Date
- Jun-2015
- Publisher
- The Institute of Electronics, Information and Communication Engineers (IEICE)
- Keywords
- Cryptography; Field-Programmable Gate Array (FPGA); Hardware implementation; Hash functions; Secure Hash Algorithm (SHA)
- Citation
- IEICE Electronics Express, v.12, no.12, pp 1 - 12
- Pages
- 12
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE Electronics Express
- Volume
- 12
- Number
- 12
- Start Page
- 1
- End Page
- 12
- ISSN
- 1349-2543
- Abstract
- In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8% over the pipeline architecture that is known to have nearly achieved the theoretical performance limit. We implemented our system on the Xilinx Virtex-6 FPGA and verified the operations by interfacing it with MicroBlaze soft processor core. © IEICE 2015.
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