Design Guideline of Saddle-Fin-Based DRAM for Mitigating Rowhammer Effect
- Authors
- Suh, Minki; Ryu, Minsang; Ha, Jonghyeon; Bang, Minji; Lee, Dabok; Kim, Jungsik
- Issue Date
- Apr-2024
- Publisher
- Institute of Electrical and Electronics Engineers
- Keywords
- Dynamic random access memory (DRAM); local substrate implant (LSI); retention; Rowhammer (RH); saddle fin; technology computer-aided design (TCAD)
- Citation
- IEEE Transactions on Electron Devices, v.71, no.4, pp 1 - 6
- Pages
- 6
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE Transactions on Electron Devices
- Volume
- 71
- Number
- 4
- Start Page
- 1
- End Page
- 6
- URI
- https://scholarworks.gnu.ac.kr/handle/sw.gnu/70030
- DOI
- 10.1109/TED.2024.3367800
- ISSN
- 0018-9383
1557-9646
- Abstract
- In this study, we investigate a novel design for a saddle-fin-based dynamic random access memory (s-fin DRAM) aimed at mitigating the Rowhammer (RH) effect. This work involves modifying the doping scheme and employing technology computer-aided design (TCAD) simulations. We propose two distinct doping schemes to counteract the RH effect within adjacent memory cells: local substrate implant (LSI) and adjusting the depth of the storage node (SN). For s-fin DRAM with LSI, we introduce an additional implant into the substrate region adjacent to the shallow trench isolation (STI) near the end of the passing gate (PG). This additional implant creates a higher conduction band energy (CBE) area, thereby reducing the electron density drawn from the SN due to the strong electric field when the PG is activated. The simulation results demonstrate that this LSI approach mitigates the RH effect by 62.7% and slightly improves the retention time, primarily owing to the lowered gate work function. A significant improvement in RH tolerance up to 2.3 times greater than that for conventional s-fin DRAM is observed for s-fin DRAM with SN depth modification. This enhancement is attributed to the increased depth of the SN, which reduces the inversion area caused by PG activation, with the depletion area closely situated near the SN junction. Furthermore, we combine LSI approach with the s-fin DRAM design featuring an increased SN depth. The findings reveal that the designed s-fin DRAM exhibits up to 3.4 times greater RH tolerance than its conventional counterpart.
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