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Control mechanism for low power embedded TLB

Authors
Lee, J.-H.
Issue Date
2012
Keywords
Low power design; Memory hierarchy; Temporal locality; Translation look-aside buffer (TLB)
Citation
Lecture Notes in Electrical Engineering, v.107 LNEE, pp 477 - 481
Pages
5
Indexed
SCOPUS
Journal Title
Lecture Notes in Electrical Engineering
Volume
107 LNEE
Start Page
477
End Page
481
URI
https://scholarworks.gnu.ac.kr/handle/sw.gnu/23241
DOI
10.1007/978-94-007-2598-0_50
ISSN
1876-1100
1876-1119
Abstract
This research proposes a new embedded translation look-aside buffer (TLB) structure that can reduce the power consumption effectively by using simple hardware control logics. The proposed TLB structure is constructed as two fully associative TLBs and one of the two TLBs is selectively accessed by the dynamic selection method. It is shown that on-chip power consumption of the proposed TLB can be reduced by around 42% comparing with the conventional fully associative TLBs with the same number of entries. ? 2011 Springer Science+Business Media B.V.
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IT공과대학 (제어로봇공학과)
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