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Design of novel 1 transistor phase change memoryopen access
- Issue Date
- 2014
- Keywords
- GST; Memory; Nonvolatile; PCM; Phase change memory
- Citation
- Transactions on Electrical and Electronic Materials, v.15, no.1, pp 37 - 40
- Pages
- 4
- Indexed
- SCOPUS
KCI
- Journal Title
- Transactions on Electrical and Electronic Materials
- Volume
- 15
- Number
- 1
- Start Page
- 37
- End Page
- 40
- ISSN
- 1229-7607
2092-7592
- Abstract
- A novel memory is reported, in which Ge2Sb2Te5 (GST) has been used as a floating gate. The threshold voltage was shifted due to the phase transition of the GST layer, and the hysteretic behavior is opposite to that arising from charge trapping. Finite Element Modeling (FEM) was adapted, and a new simulation program was developed using c-interpreter, in order to analyze the small shift of threshold voltage. The results show that GST undergoes a partial phase transformation during the process of RESET or SET operation. A large VTH shift was observed when the thickness of the GST layer was scaled down from 50 nm to 25 nm. The novel 1 transistor PCM (1TPCM) can achieve a faster write time, maintaining a smaller cell size. ? 2014 KIEEME. All rights reserved.
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Collections - 융합기술공과대학 > Division of Converged Electronic Engineering > Journal Articles
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