A hybrid PCM memory as a main memory for a next generation smart device

Abstract

Background/Objectives: Our main objective is to design a hybrid PCM memory for the substitution of a DRAM.PCM (Phase Change Memory) is a promising candidate to replace DRAM due to its non-volatile, byte-addressable access, in addition to its ability to store data without refreshing. Methods/Statistical analysis: However, PCM is unsuitable as the main memory because it has limitations: high read/write latency and low endurance. In this paper, we propose an effective memory management technique for a hybrid PCM with a DRAM buffer. We can reduce both access and write operations of PCM by using effective page replacement. For performance evaluation of the proposed algorithm we used a SPEC CPU 2006, and implement a trace driven simulation. The trace is acquired using a modified version of the Cachegrind tool from the Valgrind 3.6.3 toolset. Findings: For the performance evaluation, we determined the access ratio of PCM and the access time of the hybrid memory, and compared them with the CLOCK-DWF algorithm because it utilizes DRAM based on the write operation, just like the proposed hybrid memory. According to our simulation, the hybrid PCM can reduce the access count by approximately 66% and the access time by 22%, compared with the CLOCK-DWF algorithm. Improvements/Applications: we proposed an effective and simple page management policy for the nextgeneration hybrid memory architecture. ? 2018, Institute of Advanced Scientific Research, Inc. All rights reserved.