ScholarWorks@경상국립대학교

초록

This article proposes a power management unit (PMU) for a millimeter-scale, multilayer-stacked computing system, designed to efficiently manage significant load current variations between low-power sleep mode and high-performance active mode. The system ensures a reliable power supply across different chip layers, rapidly increasing output driving strength in response to active-mode requests from any layers. In addition, the circuit adaptively manages the switching frequency of its power converters for dynamic frequency scaling, compensating for temperature changes by using an oscillator that replicates the processor's clock. The proposed design is fabricated using a 180-nm process and integrated with other chip layers in a millimeter-scale system. The system's PMU eliminates voltage drop during transitions to active mode by utilizing a constant energy-per-cycle oscillator with a wide frequency range of 1.89 Hz-104 MHz, along with a replica oscillator of the processor. It achieves over 50% power conversion efficiency across a load power range of 41 nW-409 mu W.

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