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Back-Gate Bias-Controllable Subthreshold Slope of Junctionless Transistors
- Jeon, Dae-Young;
- Park, So Jeong;
- Barraud, Sylvain;
- Ghibaudo, Gerard
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0초록
Junctionless transistors (JLTs) are one of the next-generation logic transistors for sub-3-nm technology nodes with several advantages, including very simple structure, no p-n junctions at source and drain, and bulk conduction-based operation. In this work, back-gate voltage (V-gb) influenced subthreshold conduction mechanism of JLTs was investigated in detail. The subthreshold swing (SS) in JLTs was clearly improved with applying a negative V-gb, since the effective channel thickness of JLT was controlled by V-gb. The experimental results were verified by analytical model equations and numerical simulation. Those results provide a key information for developing low-power and energy-efficient applications with JLTs.
키워드
Transistors; Logic gates; Capacitance; Analytical models; Semiconductor device measurement; Mathematical models; Silicon; Equivalent circuits; Subthreshold current; P-n junctions; Analytical model equations; back-gate voltage (V-gb); junctionless transistors (JLTs); subthreshold conduction; subthreshold swing (SS)
- 제목
- Back-Gate Bias-Controllable Subthreshold Slope of Junctionless Transistors
- 저자
- Jeon, Dae-Young; Park, So Jeong; Barraud, Sylvain; Ghibaudo, Gerard
- 발행일
- 2025-07
- 유형
- Article
- 권
- 72
- 호
- 7
- 페이지
- 3903 ~ 3906