Back-Gate Bias-Controllable Subthreshold Slope of Junctionless Transistors
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초록

Junctionless transistors (JLTs) are one of the next-generation logic transistors for sub-3-nm technology nodes with several advantages, including very simple structure, no p-n junctions at source and drain, and bulk conduction-based operation. In this work, back-gate voltage (V-gb) influenced subthreshold conduction mechanism of JLTs was investigated in detail. The subthreshold swing (SS) in JLTs was clearly improved with applying a negative V-gb, since the effective channel thickness of JLT was controlled by V-gb. The experimental results were verified by analytical model equations and numerical simulation. Those results provide a key information for developing low-power and energy-efficient applications with JLTs.

키워드

TransistorsLogic gatesCapacitanceAnalytical modelsSemiconductor device measurementMathematical modelsSiliconEquivalent circuitsSubthreshold currentP-n junctionsAnalytical model equationsback-gate voltage (V-gb)junctionless transistors (JLTs)subthreshold conductionsubthreshold swing (SS)
제목
Back-Gate Bias-Controllable Subthreshold Slope of Junctionless Transistors
저자
Jeon, Dae-YoungPark, So JeongBarraud, SylvainGhibaudo, Gerard
DOI
10.1109/TED.2025.3571396
발행일
2025-07
유형
Article
저널명
IEEE Transactions on Electron Devices
72
7
페이지
3903 ~ 3906