Low-voltage operation of graphene p-n junctions on plastic substrates

초록

Minimizing the range of the applied gate bias in field-effect transistors is essential for reducing power consumption in modern electronics. In this study, we successfully realized a low-bias operating graphene p-n junction on a polyethylene terephthalate substrate by combining two distinct high-density electrostatic gating methods—ionic-liquid gating and high-κ solid-state gating—in a dual-gate configuration, requiring gate voltages as low as 2 V in both cases. This dual gating is fully reversible and stable, with no electrochemical reactions associated with the ionic liquids. The highly efficient solid-state gating is achieved using a thin high-κ aluminum oxide layer that naturally forms at the aluminum/graphene interface due to their weak bonding. Our device architecture offers an ideal platform for developing high-performance, energy-efficient 2D material-based transistors that operate at low voltages on flexible and transparent substrates.

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