ScholarWorks@경상국립대학교

초록

This paper presents an ultra-low-power CMOS voltage reference designed and verified in an 180 nm standard CMOS technology. To achieve DC and AC supply sensitivity under 0.01%/V and -100 dB, it employs a single transistor and two 2-T cores to improve supply immunity with minimal overhead, adding only one drain-to-source voltage for the total supply voltage. The proposed design achieves a line sensitivity of 0.0027%/V in a supply voltage range of 0.5 V to 2 V and consumes 630 pW with a supply voltage of 0.5 V. The simulated temperature coefficient is 12 ppm/degrees C in a temperature range of -40 degrees C to 150 degrees C, and the simulated power supply rejection ratio is -100.5 dB at 100 Hz without requiring any output decoupling capacitor.

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