Effect of Back-Gate Bias-Induced Interfaces on the Zero-Temperature-Coefficient in Fully Depleted SOI Transistors

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초록

This study investigates the impact of back-gate bias-induced interfaces on the zero-temperature-coefficient (ZTC) point in fully depleted SOI transistors, revealing its fundamental mechanism through mutual compensation between threshold voltage (V-th) shifts and interface-affected carrier mobility. Experimental results demonstrate that the ZTC point systematically tracks V-th modulation and interface effects with varying Vgb. Notably, positive V-gb significantly narrows the gap between ZTC and V-th, as the dominant conduction channel shifts toward the high-quality bottom interface with minimal interface states influence.

키워드

Temperature; Silicon-on-insulator; Back; Transistors; Electrons; Scattering; Transconductance; Fully depleted SOI transistors; zero-temperature-coefficient (ZTC); back-gate bias; ZTC modulation; interface states
제목
Effect of Back-Gate Bias-Induced Interfaces on the Zero-Temperature-Coefficient in Fully Depleted SOI Transistors
저자
Jeon, Dae-Young; Kim, Yeonsu; Casse, Mikael; Nicoletti, Sergio; Kim, Gyu-Tae
DOI
10.1109/JEDS.2026.3717628
발행일
2026-08
유형
Article
저널명
IEEE Journal of the Electron Devices Society
권
14
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