A 28 nm 66.8 TOPS/W Sparsity-Aware Dynamic-Precision Deep-Learning Processor

  • Mun, HanGyeol; 
  • Son, Hyunwoo; 
  • Moon, Seunghyun; 
  • Park, Jaehyun; 
  • Kim, ByungJun; 
  • 외 1명
Citations

SCOPUS

12

초록

The required precision for deep neural network (DNN) models strongly depends on sparsity and compactness. This paper presents a heterogeneous DNN accelerator performing dynamic-precision computing adapted to sparsity. Simulation shows that the proposed dynamic precision computing successfully covers EfficientNets and Transformers with a negligible accuracy loss. The accelerator, fabricated in a 28nm LP CMOS, achieves a peak energy efficiency of 66.8 TOPS/W with a peak performance of 4.2 TOPS. © 2023 JSAP.

제목
A 28 nm 66.8 TOPS/W Sparsity-Aware Dynamic-Precision Deep-Learning Processor
저자
Mun, HanGyeol; Son, Hyunwoo; Moon, Seunghyun; Park, Jaehyun; Kim, ByungJun; Sim, Jae-Yoon
DOI
10.23919/VLSITechnologyandCir57934.2023.10185264
발행일
2023-07
유형
Conference paper
저널명
Digest of Technical Papers - Symposium on VLSI Technology
권
2023-June