첨단 반도체 패키징의 열관리 및 열-기계 신뢰성을 위한 재료 기술의 최근 연구 동향

초록

With the widespread adoption of 2.5D and 3D integration, chiplet architectures, and high-bandwidth memory (HBM) stacking, the performance limitations of advanced semiconductor packages can no longer be understood solely in terms of package architecture. The material stack within a package—including substrates, dielectrics, bonding layers, encapsulants, and thermal interface materials—critically governs both thermal resistance and thermomechanical stress. In particular, the low thermal conductivity of polymers, interfacial thermal boundary resistance (TBR), and coefficient of thermal expansion (CTE) mismatch induce warpage, delamination, and cracking, thereby limiting system reliability. After briefly outlining the relevant package architectures, this review presents an integrated, materials-oriented framework for evaluating heat transfer and thermomechanical reliability. Specifically, this review examines the key trade-offs among heat transfer, processability, and thermomechanical reliability in polymer-based thermal interface materials (TIMs); underfills and epoxy molding compounds (EMCs); polymer dielectrics and photosensitive polyimides (PSPIs) for redistribution layers (RDLs); glass substrates and through-glass vias (TGVs); and Cu–Cu direct and Cu/dielectric hybrid bonding. Particular emphasis is placed on interface engineering and reliability modeling for ultrathin bond lines and densely stacked structures. Finally, this review identifies materials-driven thermal–mechanical co-design that integrates materials, processes, and interfaces as a key research direction for next-generation advanced packaging.

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