ScholarWorks@경상국립대학교

초록

This paper presents an analog delay-locked loop (DLL) with a digital coarse lock and error compensation, designed to enhance locking speed in duty-cycled operation while ensuring reliability. To accelerate coarse locking speed and prevent coarse lock failure, the proposed DLL combines a low-resolution digital-to-analog converter (DAC) with an analog method for accurate lock range identification, efficiently handling scenarios where the DAC's limited resolution could lead to failure. Additionally, it enables the rapid control of voltage adjustments by disconnecting a loop filter during the coarse lock, eliminating the need for a buffer. The DLL improves the coarse lock process reliability by compensating for potential false lock errors caused by circuit non-idealities, such as residual RC delay and amplifier offset. Furthermore, it reuses the previously identified DAC input for the duty-cycled operation to significantly reduce relock time. To mitigate the risk of potential false lock resulting from changes in locking conditions, it can update the previous DAC input upon relocking, ensuring more reliable relocking. The proposed DLL, implemented in a 28 nm CMOS process, reduces initial lock and relock times by an average of 49.3% and 65.9% at a supply voltage of 0.5 V, and 42.4% and 70.2% at 1 V, respectively, compared to the conventional analog DLL.

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