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Reliability and Maintainability Evaluation of MVDC Submodule Test Evaluation System by Fault-Tree Analysis and Critical Maintenance Time Estimation

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dc.contributor.authorCha, Jae-Hun-
dc.contributor.authorLee, Sang-Hyeok-
dc.contributor.authorSong, Sung-Geun-
dc.contributor.authorKang, Feel-Soon-
dc.date.accessioned2025-11-05T08:00:09Z-
dc.date.available2025-11-05T08:00:09Z-
dc.date.issued2025-10-
dc.identifier.issn2169-3536-
dc.identifier.issn2169-3536-
dc.identifier.urihttps://scholarworks.gnu.ac.kr/handle/sw.gnu/80654-
dc.description.abstractThis paper proposes a new RAM analysis method to evaluate a submodule test system’s Reliability, Availability, and Maintainability for MVDC in the early design stage. To reflect the risk according to the operating characteristics of the so-called Dual-mode test circuit (DTC) combined with the half-bridge submodule, the Mean Time to Failure (MTTF) and failure rate are derived using Fault-Tree Analysis (FTA). Considering the characteristics of the early design stage, where maintenance information is insufficient, the allowable limit of the essential maintenance time is inferred by applying the standardized test method and Operating Characteristic (OC) curve step by step. Finally, the minimum MTTF value to achieve the target availability is determined. The proposed RAM analysis method can provide a valuable guideline for evaluating a system’s Reliability, Availability, and Maintainability (RAM) in the early design stage.-
dc.format.extent13-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleReliability and Maintainability Evaluation of MVDC Submodule Test Evaluation System by Fault-Tree Analysis and Critical Maintenance Time Estimation-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/ACCESS.2025.3620283-
dc.identifier.scopusid2-s2.0-105019492953-
dc.identifier.wosid001596883500050-
dc.identifier.bibliographicCitationIEEE Access, v.13, pp 177932 - 177944-
dc.citation.titleIEEE Access-
dc.citation.volume13-
dc.citation.startPage177932-
dc.citation.endPage177944-
dc.type.docTypeArticle-
dc.description.isOpenAccessY-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaTelecommunications-
dc.relation.journalWebOfScienceCategoryComputer Science, Information Systems-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryTelecommunications-
dc.subject.keywordAuthorDual-mode test circuit (DTC)-
dc.subject.keywordAuthorfault-tree analysis (FTA)-
dc.subject.keywordAuthormean time to failure (MTTF)-
dc.subject.keywordAuthormedium voltage direct current (MVDC)-
dc.subject.keywordAuthoroperating characteristic (OC) curve-
dc.subject.keywordAuthorRAM (reliability, availability, and maintainability)-
dc.subject.keywordAuthorsubmodule-
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