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From Timed Automata to Go: Formally Verified Code Generation and Runtime Monitoring for Cyber-Physical Systems

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dc.contributor.authorCho, Soomin-
dc.contributor.authorKang, Inhye-
dc.contributor.authorKim, Jin Hyun-
dc.date.accessioned2025-09-24T01:30:12Z-
dc.date.available2025-09-24T01:30:12Z-
dc.date.issued2025-09-
dc.identifier.issn2169-3536-
dc.identifier.issn2169-3536-
dc.identifier.urihttps://scholarworks.gnu.ac.kr/handle/sw.gnu/80142-
dc.description.abstractThe design of critical components in cyber-physical systems (CPS) demands rigorous guarantees of safety and correctness, particularly in safety-critical domains such as autonomous vehicles and industrial automation. While formal verification techniques, such as Timed Automata (TA) models analyzed with UPPAAL, provide strong offline assurances, transitioning these models into reliable executable systems remains a major challenge, especially when integrated with unverified legacy systems. This paper shows that combining formal verification with runtime monitoring can effectively bridge this gap and enhance system reliability. We introduce a novel framework that automatically translates UPPAAL-verified TA models into executable Go programs, leveraging a new intermediate formalism, Timed Automata with Disjoint Actions (TADA), to make time progression explicit and resolve semantic ambiguities in code generation. By integrating lightweight runtime monitors into the generated code, our approach ensures continuous enforcement of timing invariants even when verified components interact with legacy elements. Compared to prior work focused solely on offline verification, our hybrid approach offers a robust safety envelope in heterogeneous environments. We demonstrate the effectiveness of our framework through a case study on an industrial control system, showing that it successfully detects and mitigates timing violations introduced by legacy components, significantly improving overall system resilience.-
dc.format.extent21-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleFrom Timed Automata to Go: Formally Verified Code Generation and Runtime Monitoring for Cyber-Physical Systems-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/ACCESS.2025.3608215-
dc.identifier.scopusid2-s2.0-105015459572-
dc.identifier.wosid001579074200013-
dc.identifier.bibliographicCitationIEEE Access, v.13, pp 161729 - 161749-
dc.citation.titleIEEE Access-
dc.citation.volume13-
dc.citation.startPage161729-
dc.citation.endPage161749-
dc.type.docTypeArticle-
dc.description.isOpenAccessY-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaTelecommunications-
dc.relation.journalWebOfScienceCategoryComputer Science, Information Systems-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryTelecommunications-
dc.subject.keywordAuthorautomatic code generation-
dc.subject.keywordAuthorcyber physical systems-
dc.subject.keywordAuthorformal verification-
dc.subject.keywordAuthortimed automata-
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