Design of Sub-THz Low-Power and High-Gain Amplifiers Based on Double-Embedded Technique

Abstract

This article presents a sub-THz low-power and high-gain amplifier design technique based on a double-embedded pseudo-G(max)-core. The implementation of the double-embedded pseudo-G(max) -core adopts an additional linear, lossless, and reciprocal (LLR) network that satisfies theG(max)-condition for any even or odd number of N-stage cascaded transistor-level pseudo-G(max)-cores which have a stability factor and phase delay of 1 and 2m pi/N, respectively. By utilizing the proposed double-embedded pseudo-G(max)-cores, the amplifiers can achieve a higher gain with a reduced dc power consumption compared to the previously reported double-G(max) core-based amplifier, which can only employ an even number of stages. For proof of concept, two amplifiers are implemented in a 65-nm CMOS process which achieve power gain of 18.2 and 9.3 dB and gain-per-mW of 1.48 and 1.4 dB/mW at 280.2 and 309.2 GHz, respectively.