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Cited 13 time in webofscience Cited 14 time in scopus
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Molecular Engineering of Printed Semiconducting Blends to Develop Organic Integrated Circuits: Crystallization, Charge Transport, and Device Application Analyses

Authors
Kwon, Hyeok-jinTang, XiaowuKim, SeonghyeonLi, ZhijunWang, RixuanPark, Byung HoKim, CheulhwanKim, SoyeonHong, JisuRyu, Ka YeonChoi, Hyun HoAn, Tae KyuLee, JihoonKim, Se Hyun
Issue Date
May-2022
Publisher
American Chemical Society
Keywords
organic field-effect transistors; organic semiconductors; electrohydrodynamic jet printing; integrated devices; printed electronics
Citation
ACS Applied Materials & Interfaces, v.14, no.20, pp 23678 - 23691
Pages
14
Indexed
SCIE
SCOPUS
Journal Title
ACS Applied Materials & Interfaces
Volume
14
Number
20
Start Page
23678
End Page
23691
URI
https://scholarworks.gnu.ac.kr/handle/sw.gnu/71654
DOI
10.1021/acsami.2c02032
ISSN
1944-8244
1944-8252
Abstract
Solution-based printing has contributed to the facile deposition of various types of materials, including the building blocks of printed electronics. In particular, solution-processable organic semiconductors (OSCs) are regarded as one of the most fascinating candidates for the fabrication of printed electronics. Herein, we report electrohydrodynamic (EHD) jet-printed p- and n-type OSCs, namely 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-PEN) and 6,13-bis((triisopropylsilyl)ethynyl)-5,7,12,14-tetraazapentacene (TIPS-TAP), and their use as single-OSC layers and as OSC mixed p-n layers to fabricate solutionprocessed p-, n-, and ambipolar-type organic field-effect transistors (OFETs). Use of the dragging mode of EHD jet printing, a process driven under a low electrostatic field with a short nozzle-to-substrate distance, was found to provide favorable conditions for growth of TIPS-PEN and TIPS-TAP crystals. In this way, the similar molecular structures of TIPS-PEN and TIPS-TAP yielded a homogeneous solid solution and showed ambipolar transport properties in OFETs. Therefore, the combination of single- and mixedOSC layers enabled the preparation of various charge-transported devices from unit to integrated devices (NOT, NAND, NOR, and multivalued logic). Therefore, this fabrication technology can be useful for assisting in the production of OSC layers for practical applications in the near future.
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