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Cited 12 time in webofscience Cited 11 time in scopus
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Wafer-scale and environmentally-friendly deposition methodology for extremely uniform, high-performance transistor arrays with an ultra-low amount of polymer semiconductors

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dc.contributor.authorCho, Jangwhan-
dc.contributor.authorKo, Yeongun-
dc.contributor.authorCheon, Kwang Hee-
dc.contributor.authorYun, Hui-Jun-
dc.contributor.authorLee, Han-Koo-
dc.contributor.authorKwon, Soon-Ki-
dc.contributor.authorKim, Yun-Hi-
dc.contributor.authorChang, Suk Tai-
dc.contributor.authorChung, Dae Sung-
dc.date.accessioned2022-12-26T22:47:54Z-
dc.date.available2022-12-26T22:47:54Z-
dc.date.issued2015-03-
dc.identifier.issn2050-7526-
dc.identifier.issn2050-7534-
dc.identifier.urihttps://scholarworks.gnu.ac.kr/handle/sw.gnu/18537-
dc.description.abstractWe report on a new class of microliter-scale solution processes for fabricating highly uniform and largearea transistor arrays with extremely low consumption of semiconducting polymers. These processes are accomplished by applying a vertical phase separation of polymers with an environmentally benign solvent, a random copolymerization strategy between two highly conductive repeating units, and a meniscus-dragging deposition technique. The successful realization of these three processes, as confirmed by the structural and morphological in-depth characterizations, has enabled the fabrication of high-performance polymeric field-effect transistors that were uniformly distributed, without a single failure, on a 4 inch wafer using only 40 mu g of semiconducting polymers. The resulting transistor arrays showed an average mobility of 0.28 cm(2) V-1 s(-1), with a low standard deviation of 0.04, as well as ultra-uniform near-zero threshold voltages. Our simple strategy shows great promise for fabricating large-scale organic electronic devices in the future using a truly low-cost process.-
dc.format.extent6-
dc.language영어-
dc.language.isoENG-
dc.publisherRoyal Society of Chemistry-
dc.titleWafer-scale and environmentally-friendly deposition methodology for extremely uniform, high-performance transistor arrays with an ultra-low amount of polymer semiconductors-
dc.typeArticle-
dc.publisher.location영국-
dc.identifier.doi10.1039/c4tc02674h-
dc.identifier.scopusid2-s2.0-84924941859-
dc.identifier.wosid000351459300017-
dc.identifier.bibliographicCitationJournal of Materials Chemistry C, v.3, no.12, pp 2817 - 2822-
dc.citation.titleJournal of Materials Chemistry C-
dc.citation.volume3-
dc.citation.number12-
dc.citation.startPage2817-
dc.citation.endPage2822-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClasssci-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaMaterials Science-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryMaterials Science, Multidisciplinary-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordPlusFIELD-EFFECT TRANSISTORS-
dc.subject.keywordPlusHIGH-MOBILITY-
dc.subject.keywordPlusLARGE-AREA-
dc.subject.keywordPlusCHARGE-TRANSPORT-
dc.subject.keywordPlusDISORDER-
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