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Cited 2 time in webofscience Cited 3 time in scopus
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Compositional power-aware real-time scheduling with discrete frequency levels

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dc.contributor.authorTchamgoue, Guy Martin-
dc.contributor.authorSeo, Junho-
dc.contributor.authorKim, Kyong Hoon-
dc.contributor.authorJun, Yong-Kee-
dc.date.accessioned2022-12-26T21:33:59Z-
dc.date.available2022-12-26T21:33:59Z-
dc.date.issued2015-08-
dc.identifier.issn1383-7621-
dc.identifier.issn1873-6165-
dc.identifier.urihttps://scholarworks.gnu.ac.kr/handle/sw.gnu/17105-
dc.description.abstractPower consumption remains a hot issue in all areas of computing ranging from embedded systems that rely on batteries to large scale data centers where reducing the power consumption of computing devices directly affects not only the management cost, but also contributes to a greener computing environment. The power-aware real-time scheduling problem has recently been addressed for a compositional framework with periodic task model under the assumption that a processor can continuously vary its operating frequency and voltage. However, in practice, this technique is only suboptimal and still produce the waste of computational resources. This paper introduces new frequency scaling schemes that statically determine optimal processor speeds at system, component, and task levels with the objective of minimizing the total energy consumption of the entire framework. Since real-world processors support only a finite set of operating frequencies, our algorithms also consider only discrete speed levels and guarantee still that each task meets its deadline. We implemented and evaluated the performance of a prototype framework that incorporates our algorithms on top of the RT-Xen hypervisor in order to provide power-aware compositional real-time scheduling framework to virtual machines. (C) 2015 Elsevier B.V. All rights reserved.-
dc.format.extent13-
dc.language영어-
dc.language.isoENG-
dc.publisherELSEVIER SCIENCE BV-
dc.titleCompositional power-aware real-time scheduling with discrete frequency levels-
dc.typeArticle-
dc.publisher.location네델란드-
dc.identifier.doi10.1016/j.sysarc.2015.05.003-
dc.identifier.scopusid2-s2.0-84936755276-
dc.identifier.wosid000359033000001-
dc.identifier.bibliographicCitationJOURNAL OF SYSTEMS ARCHITECTURE, v.61, no.7, pp 269 - 281-
dc.citation.titleJOURNAL OF SYSTEMS ARCHITECTURE-
dc.citation.volume61-
dc.citation.number7-
dc.citation.startPage269-
dc.citation.endPage281-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryComputer Science, Software Engineering-
dc.subject.keywordPlusFRAMEWORK-
dc.subject.keywordPlusENERGY-
dc.subject.keywordPlusTASKS-
dc.subject.keywordAuthorCompositional real-time scheduling-
dc.subject.keywordAuthorPeriodic resource model-
dc.subject.keywordAuthorPeriodic task model-
dc.subject.keywordAuthorPower-aware scheduling-
dc.subject.keywordAuthorDVFS-
dc.subject.keywordAuthorDiscrete frequencies-
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