Low-Temperature, Solution-Processed, 3-D Complementary Organic FETs on Flexible Substrate

Abstract

Vertical stacking of thin-film transistors is an effective way to reduce the footprint of a device, thus increases transistor density in complex flexible electronic applications without reducing the feature size and resolution of the patterning tools. In this paper, we report a 3-D complementary organic FET fabricated on a plastic substrate by stacking a bottom-gate top-contact p-type transistor on a top-gate bottom-contact n-type transistor with a gate shared between the two. We used high-performance polymer semiconductors, poly [(E)-2, 7-bis (2 decyltetradecyl) 4 methyl 9 (5 (2 (5 methylthiophen 2 yl) vinyl) thiophen 2 yl) benzo [lmn] [3, 8] phenanthroline-1, 3, 6, 8 (2H, 7H)-tetraone] for n-type devices and poly [2, 5-bis (7-decylnonadecyl) pyrrolo [3, 4-c] pyrrole-1, 4 (2H, 5H)-dione-(E) 1,2 bis (5 (thiophen 2 yl) selenophen 2 yl) ethene] for p-type devices to fabricate the vertically stacked organic transistors along with a Cytop and cross-linked poly (4-vinylphenol) bilayer and Poly (Methyl Methacrylate) gate dielectric. A 3-D flexible complementary organic inverter exhibits a maximum static voltage gain of approximate to 18 V/V and high noise immunity of up to 60% of V-DD/2. The 3-D transistors show hysteresis-free I-V characteristics despite of low-temperature processes. Moreover, we discuss the influence of cross-linker concentration and the processing temperature of the PVP dielectric film on the degree of hysteresis in I-V characteristics.