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A 0.055 mm<SUP>2</SUP> Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9-6.1 GHz Frequency Tuningopen access

Kang, Byeongseok; Kim, Youngsik; Son, Hyunwoo; Kim, Shinwoong

ArticleIssue Date2024CitationELECTRONICS, v.13, no.13PublisherMDPI
SCIESCOPUS
A Fully Synthesizable Fractional-N Digital Phase-Locked Loop with a Calibrated Dual-Referenced Interpolating Time-to-Digital Converter to Compensate for Process–Voltage–Temperature Variationsopen access

Kim, Seojin; Kim, Youngsik; Son, Hyunwoo; Kim, Shinwoong

ArticleIssue Date2024CitationElectronics (Switzerland), v.13, no.18PublisherMultidisciplinary Digital Publishing Institute (MDPI)
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